Interrupt techniques are frequently used in many existing computer system technologies. Generally, an interrupt can be described as an asynchronous event that suspends normal processing and temporarily diverts processor control to process (or handle) the interrupt. Many contemporary computer systems employ a message signaled interrupt (MSI) process or an input-output advanced programmable interrupt controller (IO APIC). Message signaled interrupts are a type of edge triggered interrupt (as opposed to level triggered interrupts) and can be viewed as a discrete interrupting event. A conventional technique for dealing with MSIs is specified in the Advanced Programmable Interrupt Controller (APIC) standard. This standard is used primarily in multiprocessor systems and supports interrupt redirection and interrupt transmission between processors.
In conventional APIC techniques, the processor being interrupted responds to an interrupt by storing information about the current state of the running program and invoking a first-level interrupt handler (commonly referred to as an Interrupt Service Routine (ISR)). The ISR may then call another interrupt handler associated with the particular device that generated the interrupt (i.e., a device driver for the particular device) to discover the cause of the interrupt. In the case of a shared interrupt, the device driver of the device normally reads the device interrupt status to identify whether it should claim (service) the interrupt. If the device is the source of the interrupt, the device driver performs certain critical tasks to minimize interrupt handling time, and then schedules a deferred procedure call (DPC), which represents the instructions necessary to actually service the interrupt. The device driver next sets a flag to tell the ISR that its device is the owner of (claims) the interrupt. If the device driver doesn't claim the interrupt, the device driver exits without setting the flag and the ISR continues to call the interrupt routine of other device drivers to service the interrupt.
However, the communication necessary to identify the device that has generated the interrupt may produce interrupt handling latencies. That is, the various communication paths between the ISR, device driver(s) and the DPC may be extensive. This is particularly apparent where interrupts are shared by multiple devices since the device drivers need to be successively activated. As a consequence the operating speed of the computer system may be significantly affected.